1. Field of the Invention
The present invention relates to circuitry for transmitting electrical signals from one location to another. In particular, the present invention relates to output drivers designed to provide timely transmission of such signals at required potentials and with sufficient current for communications between coupled devices. Still more particularly, the present invention relates to circuitry for regulating the transition of logic signals between xe2x80x9chighxe2x80x9d and xe2x80x9clowxe2x80x9d levels, including those associated with Complementary Metal-Oxide-Silicon (CMOS) transistor-based output drivers.
2. Description of the Prior Art
Output drivers are used to transfer electrical signals of desired amplitude and strength. Signal transfers occur by way of busesxe2x80x94interfaces that couple active devices that are either on the same semiconductor-based chip or on different chips. The devices may be located proximate to one another, or they may be some distance from one another. One example of a proximate device interface requiring one or more bus connections is the coupling of one printed circuit board to another within a computing system, such as through a backplane bus. An example of a remote device interface requiring one or more bus connections is the coupling of one computing system to another, such as through a telephone transmission line that is, effectively, a voice/data bus.
A continuing goal in all computing and communication systems is to be able to transfer electrical signals accurately and as quickly as possible. In order to achieve that goal, it is important that those signals are transmitted at relatively uniform rates, amplitudes, and strengths. This is more likely to occur within a single computing system, less so when interfacing of a plurality of non-uniform computing systems is involved. Protocols have been developed to provide for transmission rate, amplitude, and strength uniformity so as to develop compatibility between systems and between sub-systems.
Since different active devices operate at different rates, e.g., printers versus memory devices, and have different load drains as a function of internal operations, each device requires one or more output drivers to meet transmission uniformity requirements. Output drivers are needed to increase signal gain prior to output to a bus, they are required to slow or increase the transmission rate of a signal to be delivered, or a combination of the two. It is to be understood that these xe2x80x9coutputxe2x80x9d drivers may also operate to receive transmissions from the bus for delivery back to the active device for interpretation and action, if any. Given this dual operation capability, these unifying drivers are generally identified as transceivers.
It is well known that in digital systems the signals moving between devices are categorized as either logic level high (or xe2x80x9c1xe2x80x9d or xe2x80x9cONxe2x80x9d) and logic level low (or xe2x80x9c0xe2x80x9d or xe2x80x9cOFFxe2x80x9d). The particular signal potential that defines whether a logic high or a logic low is being transmitted is dependent upon the semiconductor components that form the circuitry associated with that transmission. The most common circuit configurations used to produce digital signals include, among others, CMOS, Transistor-Transistor:Logic (TTL), and Emitter-Coupled Logic (ECL)xe2x80x94positive ECL (PECL) in particular. Each of these logic configurations operates differently as a function of the xe2x80x9cswingxe2x80x9d between what constitutes a logic high signal and what constitutes a logic low signal.
For CMOS logic, which is based primarily on the use of MOS transistors, a logic low signal is generally developed in the range of 0.6 volts (V) above a low-potential power rail GND, which may be at 0.0V. A logic high signal is generally developed in the range of Vcc to Vcc-0.6V, where Vcc may vary between 4.5V and 5.5V for a nominal 5-volt supply, or between 3.0V and 3.6V for a nominal 3.3-volt supply. For a 5-volt supply then, the differential swing between low and high must be at least 3.9 volts in order to ensure that a desired shift between a logic low and a logic high will occur. TTL and ECL logic configurations, on the other hand, are based primarily on the use of bipolar transistors. The differential swing for a shift between a logic low and a logic high is significantly less than it is for CMOS operation-it may as low as 1.0 volt. For PECL systems, for example, the swings are even closer. In PECL circuitry, which is Vcc dependent, a logic high is equivalent to a potential of about Vcc-0.9V, and a logic low is equivalent to a potential of about Vcc-1.7V. Thus, in mating CMOS and non-CMOS transmissions, it can be seen that variations in potential swings will not automatically ensure the triggering of a desired swing from one logic level to another. Furthermore, minor potential swings in CMOS signals may not effect any logic level change therein; however, they may be significant enough to cause an unexpected change in a TTL or an ECL logic value when transmitted to a TTL- or an ECL-based system.
Clearly, unexpected changes in logic values are not desirable. They can cause significant operational errors. Therefore, it is important to provide a transceiver driver that will not generate excessive signal potential swingsxe2x80x94other than those specifically desired to achieve a logic level shift. This problem is more likely to occur as transmission rates are increased. Increasing transmission rates enables the transfer of more data in a shorter time period and so is desirable in many respects. However, the gain in increased transmission rate is often undermined by an increase in signal noise. That is, a rapid change in signal level creates an oscillation about the steady state value corresponding to the sudden switching on or off of a transistor. The extent of the oscillation is dependent upon the particular transistor system used as well as the loading on the backplane bus.
As transistors become increasingly smaller in order to achieve the faster transmission rates of interest, the corresponding differential swings associated with their logic outputs are reduced. When the wider-swing CMOS logic systems interface with smaller-swing bipolar-transistor-based logic systems the noise associated with CMOS operation may generate enough of a swing to cause an undesired transistor switching. The signal bounce that occurs with the rapid switching often creates reflections in transmission media, such as telephone transmission lines where reflections will cause signal errors. It is therefore important to enable xe2x80x9cgentlexe2x80x9d switching of driver transistors so that signal noise is reduced when logic levels are changed.
One means for achieving some success in smoothing signal transitions in a transceiver driver has been described in U.S. Pat. No. 5,557,223 issued to Kuo. As illustrated in FIG. 1, a CMOS-based signal output driver 10 includes means intended to induce gentle switching of signal transmission. The Kuo driver includes first inverter stage 20, formed of first inverter I1 for receiving an incoming signal INPUT that is to be transmitted, and second inverter I2. Those components, along with third inverter stage 13, current mirroring transistors M199 and M197, and output transistor M202 are all relatively standard components of an output driver for delivering output signal OUTPUT. Transistors M197 and M199 are always on, as can be seen from their coupling and the use of temperature-compensation gate drivers TCD1 and TCD2, respectively. The Kuo circuit further includes discharge circuit 30 that is coupled to the gate of transistor M202 for the purpose of slowing the switching of that output transistor so that signal bounce and reverberation may be minimized. Discharge circuit 30 includes first discharge transistor M440, second discharge transistor M441, and inverter I4.
The Kuo circuit 10 is designed to provide a built-in delay in the discharge of transistor M202. An input signal at node INPUT that produces a logic high at the gate of transistor M202 also produces a logic high at the gate of transistor M440. It also produces a logic low at the gate of transistor M441. The result is that transistors M202 and M440 are on, while transistor M441 is off, thereby preventing current to pass through that branch of circuit 30 including M440 and M441. This situation results in a logic low signal at OUTPUT. When the input signal to circuit 10 switches to produce a logic low at the gate of M202 and a logic high at the inputs of inverter I4 and transistor M441, transistor M441 is turned on. Because of the gate delay caused by inverter I4, transistor M440 remains on. This results in a diversion of current from the gate of transistor M202 until I4 acts to switch off transistor M440, enabling complete turn off of M202.
The Kuo output driver of FIG. 1 is useful in softening the switching of output transistor M202. However, there are several deficiencies associated with the discharge circuit 30. Specifically, it is well known that there are vagaries associated with the fabrication of semiconductor devices. For active devices in particular, characteristics can vary by as much as 30% on chip and from chip to chip. Given the various steps and complexity associated with the formation of a transistor, for example, this is not surprising. Unfortunately, fabrication variations yield undesirable performance variations that are of increasing concern as components become smaller and acceptable operating ranges narrow. Given the introduction of transistors M440 and M441, as well as the combination of transistors and other elements likely used to create inverter I4, it is apparent that the Kuo discharge circuitry fails to address this issue. Kuo suggests that I4 may be formed of multiple inverter stages that would increase the problem. Variations in operating conditions, including temperature and supply voltages, will also effect changes in the operating performance of the Kuo transistors.
Unknown variations in operating performance are undesirable from an engineering standpoint. Instead, the designer of a transmission system requires consistency and uniformity that is likely not adequately available through the Kuo circuit. Further, the sensitivity to fabrication and environmental vagaries limit the designer""s ability to program accurately the rate of switching of the output transistor. Therefore, what is needed is a transceiver driver that will produce an output signal that is substantially independent of fabrication, temperature, and supply voltage conditions. Further, what is needed is such a transceiver driver that is reliably programmable.
It is an object of the present invention to provide a transceiver driver circuit that will produce an output signal that is substantially independent of fabrication, temperature, and supply voltage conditions. It is also an object of the present invention to provide such a circuit that is programmable.
These and other objects are achieved in the present invention through the modification of the Kuo circuit to eliminate the discharge circuit shown in FIG. 1 and adding a first discharge element for pull-up conditions and a second discharge element for pull-down conditions. The primary components of the generic output driver disclosed in FIG. 1 remain substantially the same. However, the driver of the present invention includes the noted discharge elements coupled to the inverter stage identified as inverter I3. In particular, the first discharge element is preferably coupled between the high-potential power rail Vcc and the source of transistor M201, while the second discharge element is coupled between the low-potential power rail GND and the source of transistor M198. That is, rather than a direct manipulation of the gate of output transistor M202, the present invention modifies the turning on and off of M202 by regulating the current delivered to its gate. The use of a capacitive element rather than a set of discharge transistors ensures a gradual turning on or off of the output transistors since there is no threshold voltage to be overcome for initial discharge transistor operation. That obligation can also cause some noise, although to a lesser extent.
The first and second discharge elements of the present invention are preferably formed as capacitors. Present fabrication processes permit the formation of well-defined capacitive elements that are substantially less sensitive to process, temperature, and, certainly, supply voltage, variations than are transistor systems of the type disclosed by Kuo. Further, with the availability of increasingly smaller semiconductor devices, it is possible to provide capacitive elements to the fabrication process without taking up too much space on the chip. Present fabrication processes also enable the fabrication of well-defined capacitive elements, which in turn allows the designer to program the operation of the transceiver driver with relatively tighter tolerances. It is to be noted that, with essentially a single capacitive element, variations in fabrication processes on chip and from chip to chip have less substantially effect on operational characteristics than those experienced in the Kuo design.
Therefore, the present invention permits the design of a driver with highly programmable edge rate control, which driver operation is substantially independent of fabrication, supply voltage, and temperature vagaries. These and other advantages of the present invention will become apparent upon review of the following detailed description, the accompanying drawings, and the appended claims.